Dwarkesh_Podcast_Reiner_Pope_–_Chip_design_from_the_bottom_up

0:00I'm back with Rainer Pope, who is the CEO of Maddox, which is a new AI chip company. Last time we were talking about what happens inside a data center, now I'm going to understand what happens inside an AI chip. How does a chip actually work? Full disclosure, by the way, I am an initial investor in Maddox, so hopefully you have designed a good chip. Also, if you're listening to this on an audio platform, it's much preferable to watch this Blackboard lecture.

0:27on a platform where you can see what's happening, so switch over to YouTube or Spotify. So I'll start with sort of the very smallest fundamental unit of chip design, then we'll sort of build up into what an overall, like actual production chip, what are the components of that. At the very bottom level of a chip, the primitives that we work with are logic gates, which are very simple things like and or not. And then these are connected together by wires that have to be laid out physically as metal traces on a chip.

0:57The main function that AI chips want to compute is multiplication of matrices and really inside that is the fundamental primitive is multiply accumulative just like of passive numbers. So we're going to sort of demonstrate what that calculation looks like by hand and then sort of infer what what a circuit would look like for that. It'll turn out to be sort of easiest if I do multiplication, accumulator, something like a four bit number with another four bit number.

1:28And then we're going to, the actual clearest primitive is actually multiply, accumulate. So there's a multiply these two terms. And then we're going to add in, so product of these two terms. And then we're going to add in an 8-bit number. And can I ask a clarifying question? Why is this the natural primitive for whatever computation happens inside a computer?

2:02Yeah, so there's a few reasons for this. It's a little bit more efficient, but the reason it's natural for AI chips is that if you look what's happening during a matrix multiply, what is matrix multiply in very short? There's a for loop over i and over j and over k of output i k.

2:35plus equals to input ij times other input jk. And so multiply, accumulate happens at every single step of a matrix multiply. Makes sense. And then the other observation is that the precision will almost always be higher in the accumulation step than in the multiplication step. This is maybe specific to AI chips, but you're multiplying low precision numbers, but then when you accumulate, errors accumulate quickly, and so you need more precision here.

3:05So this is why we've chosen to do a 4-bit multiplication and an 8-bit addition. Let me make sure I understood that. There's two ways to understand that. One is that the value will be larger than the inputs. And the other is that if it was a floating point number, it would be, maybe that part is less intuitive to me. But it's maybe the same principle. It is really the same principle. I guess the separate principle is that As you are summing up this number, you are summing up a whole bunch of numbers and so you got a lot of rounding errors accumulating. Whereas in this case, there's like there's there's only one multiplication in that chain and so there's not a lot of rounding errors accumulating in the multiplication. Why are you summing up a whole bunch of numbers? There's just two numbers. I mean this summation happens. It's repeated. So yeah, any errors accumulate I see. So how would we perform this calculation by hand? I mean as a human we would probably separate it into two, but we can sort of do it all in one.

4:01using long multiplication. So the multiplication term first, we're going to multiply this number, this 4-bit number here, by every single bit position in the other 4-bit number. So we write that out. First 1001 multiplied by this bit position, that is this number itself, then shift it across by one, we're multiplying by zero. That gives us an old zeroes number.

4:31shifted across even one more to multiply by this one, we get 1001. And then finally, for this last bit position, we get an old zeroes number again. So this sort of gives us a bunch of terms that we're going to have to add for the multiplication. And then while we're doing that summation of this, we might as well add in the actual accumulated term as well. So we just copy that directly across.

5:09So this is the sum. It's a five-way sum that we're going to want to compute. So firstly, what logic gates did it take us to even get to this intermediate step? We needed to produce all 16 of these partial products. How do I produce one of these partial products? So let's take this number one, for example, here. It is one. So how do we produce this number by multiplying this number by this one over here?

5:42We can actually produce that by an AND gate. This number is 1. If both this bit is 1 and this bit is 1, if either of them is 0, then the multiplication of 0 times anything is 0. So to produce all of this stuff, we ended up consuming 16 AND gates. Or in the general case, if I were doing a p-bit multiply times a q-bit multiply, then this will be p times q.

6:14Many ands. Finally I sum them. Actually most of the work is going to happen in the summing. And so let me describe sort of the other logic gate that we use here. And is almost the simplest logic gate that exists on a chip. It's almost the smallest. At the other extreme, typically the very largest logic gate that you'll use is something called a full adder.

6:47And what this does is sort of it does, like coming from software, you might think that a full adder like adds 32-bit numbers together. In this case, it just adds three single-bit numbers together. And so you can think of it as like adding zero, one, and one together. Now, when I add these together, the result can be zero, one, two, or three. So I can express that in binary using just two bits. So it has input, it has three bits, and as output, it has two bits, which in this case, the number two in binary is one, zero.

7:17So this is also known as a three to two compressor, because it takes three bits of input and produces two bits of output. The two inputs are an X and a Y value, and then some carry that came in from like. The three inputs are all bits that are in the same sort of bit position, like three bits that are in a column here. And then the two outputs.

7:48I have sort of drawn them vertically here and horizontally here to kind of match this vertical versus horizontal layout here, which is expressing that things that are in the same column are in the same bit position. Whereas things that are in adjacent columns, this is a carry out whereas this was a sum. So if the inputs in the full adder are, let's say like 101, then the output would still be 10. If it was 111, it'd be 11.

8:12It was 0, 0, 0. It'd be 0, 0. It was like 0, 1, 0. It'd still be 0, 1. So yeah, it's just counting essentially the number of things and expressing that in binary. So this circuit actually can sort of capture what we as humans naturally do when we're doing summing along a column. So I'll show sort of one iteration of using the full adder to sum.

8:37The way I sum here is going to be a little bit unnatural for humans. Humans, we would sort of sum along the column and then remember the carry, but instead of remembering the carry, we'll actually just explicitly write it out. So in this, we proceed from the rightmost column towards the left. On the rightmost column, we sum the one and the one, and that produces like a zero here and a carry of one. So we've sort of used a this full adder circuit on this pair of bits and produced a pair of bits as output. Now we can do the same thing with this column. We've got a column of one, two, three, four numbers. And so maybe we'll take the first three of them, run a full adder on them, and that gives us a zero and a zero as output. So some of these is zero, zero. So that's the full adder applied to all of these bits. As I've used up bits, I'm gonna just cross them out to indicate that I've handled them.

9:36Let's just keep going a little bit more, so we'll go here. I take these three numbers, I add them, that gives me a one and a zero. I've dealt with these three numbers, and now I take one, two, and I can even take these three numbers, for example, right now, and add them, and that gives me a one and a zero, and I've dealt with these numbers. So.

10:00I can sort of like the way I should view this is that I have this whole grid of numbers that need to be added. I'm going to just keep applying full adders to all the bits that are here, constantly removing three numbers from a column and then writing out two numbers as output. Keep going with this over and over and over and again until I eventually get like some just one single number coming out here. Something like that. This is probably the wrong sum. So this approach that I've described here, this is called a.

10:32data multiplier, and this is sort of like the standard for how you do area efficient multipliers using full adders. Let's try and quantify the circuit size of this just so we have got a sense of like how big things are that so we can compare to them later. How many full adders do I use? I started with how many numbers? I have the 16 partial products, which is the product of all of these terms with all of these terms, plus the 8 terms that I'm adding here. So I started off with 24 bits and then I produced eight bits on the output eventually. And in every step, I was sort of crossing off three numbers and writing two numbers out as a result. And so every single use of a full adder eliminates one of the bits here. And so how many full adders it must be the 24 minus the eight. So there were 16 full adders in this circuit.

11:40In general, this is true in the general case as well. There will be p times q many full headers in this circuit. Let me try to understand the logic of that. So the input bits 24 is p times q plus p plus q. That's right. And the output bits is just p plus q. And so p times q plus p plus q minus p plus q equals p times q. That's right.

12:10So I think this explains sort of or at least hints at the second reason why we chose to do a multiplier accumulate. First reason being that's actually what shows up in matrix multiplication. But second reason being it gave us this very slick p times q very simple algebra. So we've sort of.

12:29described, like this whole procedure, every single atomic step that I took here becomes a logic gate, and then sort of the wires connected together. Like when I had these three inputs that I salvaged to produce these two outputs, like if I think of mapping this to a physical device, there would be a wire that runs sort of connecting all three of these things together into a logic gate that produced this output. Okay, so this is the main primitive at different bit widths.

13:00that is inside an AI chip. We're going to build up from here to how would you use that to run all of the other operations you may want? This might be the wrong time to ask this question, but whenever NVIDIA reports that this chip can do X many FP4 or half as many FP8, it seems to imply that those circuits are fungible, that there's not as dedicated like FP4 versus FP8. But the way you're mapping it out here, it seems like You would need, if it has to be mapped out in the logic, you would need a dedicated FP4 multiply accumulate and a dedicated FP8 accumulate. Basically, can you can you funge them? As drawn, they're actually not particularly fungible. This is actually one of the main choices you have to make when designing a chip, which is how much of FP4, how much of FP8 do I have? And then sometimes I'll make that consideration from the point of view of like, what do I think the.

13:57is the customer requirement. Another way to take an angle on that is to say what is the power budget for, equalize the power budget between FP4 and FP8. But so then when they report those numbers, and they just happen to be the case that like it does two X as many FP4 as FP8, they just happen to choose like give equivalent die areas to all the floating points and as a result that end up being Why is the ratio exactly two X? Yeah, exactly. Yeah. So part of it is, I mean, surely that wouldn't be exactly equivalent to die area. There's a data movement reason, actually, and we'll maybe come back to this when we sort of look through how it goes into another memories. There's something really nice just from a software level of the fact that I can pack two four bit numbers into the same storage as an eight bit number. And so when I store that to a memory or something like that, it's the sizing of the

14:50the buses that I wire out within the chip actually makes that work out really, really nicely. I should come to think of it. It's not just 2X. The amount of area it takes, it sounds like, is quadratic. It's quadratic, in fact. With the bit length. So that's why smaller precision is like even more favorable than the United States. This is a really big reason. So, in fact, Nvidia made a change. Historically, Up until B100 or B200 every time you have the bit precision you double the the flop count That ratio is exactly like for the reason you said because of this quadratic scaling that ratio is actually slightly wrong It should be like an even bigger you should get an even bigger speed up and then you and you might otherwise think Nvidia's like product specs have sort of started acknowledging that in B300 and beyond where the fp4 is three times faster than the fp8

15:48Though it should be 4x. Yeah, what I've shown here is like the simplest case of integer multiply. When you're dealing with floating point as you do in FP4 and FP8, there's this sort of other term which is the exponent that just complicates this calculation. So what can we see already from this? It's like I think the big observation you've made is that there's this quadratic scaling with bit width which.

16:11which is like very effective and is the single reason why low precision arithmetic has worked so well for neural nets. But the other thing we're going to do now is we're going to compare sort of the area spent on the multiplication itself with all of the circuitry that is around it. So we'll walk back in time a little bit and see how did GPUs prior to tensor cores work, which is the same way as the way that CPUs worked in fact.

16:42So which is like, where do we stick this multiply accumulate unit? So generically, I'll describe like a CUDA core or a CPU. You'll have some register file, which stores some number of entries. Maybe it's like eight entries of like, in this case, I guess four bit numbers, but typically like 32 bit numbers or something like that, which are numbers. So this is the, like, inside the CUDA core, I'll have some register file of some depth, and then I will have my multiply accumulate circuit multiply and accumulate circuit. And what it's going to do, it's going to take three arbitrary registers from this register file, perform the multiply accumulate, and then write back to the register file. So it's going to maybe write to this one, but it was able to read from this one, this one, and another random one. So it'll take three inputs like this.

17:47So this is the core data path of many processes. Most processes look like this. You've got some set of registers, and then you've got some set of logic units or ALUs. We want to analyze the cost of the data movement from the register file to the ALU and back. So ultimately, there's going to be some circuit that says, well, I don't always have to select this guy. I might select any of the registers at any point in time. And so a first question is, how can I build a circuit?

18:19The circuit that I'm going to look for is a MUX. So in this case, it's going to have eight inputs, one from each entry of the register file. And it's going to have one output which is actually producing this output. And then what is the cost of this thing? All we have to build it out of is AND and OR. And so how do we build it? We do the dumbest thing possible.

18:50Form a mask saying we okay when we want to read like the third entry We're gonna and every single entry with either one or zero based on whether that's all I want to read and then we're gonna or all of them together Okay, just to make sure I understand the basics what the mux is doing is it just like selecting just selecting just selecting an input Yeah, so like invisible to software is like you say I want input number three that means there's a mux Yeah, and so like what is the cost of this mux so an in input mux?

19:21operating on p bits, well, I'm going to, so I have n rows, that's this eight rows and I've got like each row is p bits wide. Well, I have to end every single bit. So I get n times p many and gates. Every single input I have to say, am I gonna like mask it out or not? And then I'm gonna order them all together. And so there's gonna be like n minus one times p many or gates.

19:55which is saying I've got all of these different things, almost all of them are zeros, but I need to sort of collapse them down into like from my eight options down into one option. And so every step I need to or like one row into an existing row. It's actually kind of funny that you would sort of, you don't think at the level of hardware, you sort of just think like, oh, I'll just select element three. And something as simple as that is, sort of like in and of itself a quite complicated circuit. Yeah, I mean this is the first step of all of the hidden data movement costs that the job, yeah. And so like the thing like we're just gonna like compare like I have to pay this cost and I've got one max here and then in fact I have two more copies of that for each of the three inputs to my multiply accumulate operation. And so I have this cost which is like like three times n times p and gates over here compared to this p times q like

20:52sort of gates in the actual circuit that is doing the thing I care about. And if we plug in actual numbers, like this n being 8, like I get like 24 times p, gates over just in the data movement compared to like if q is 4, like 4 times p, gates just in the multiply adder. And where is the 3 coming from? Three different inputs here. So the case, really just what I'm hinting at here is that All of this work, which scales as the size of the register file, and this is a very small register file, all of this work just moving the data from the register file to the logic unit is many, many times more expensive than the logic unit. In the most recent ClusterMax report, 79 ounces ranked almost 100 different GPU clouds. Crusoe was one of only five that made the goal tier.

21:47Semi-analysis found that gold tier providers like Crusoe had a total cost of ownership that was 5 to 15% lower than silver tier ones, even when they had identical GPU pricing. This makes sense because total cost of ownership is downstream of a bunch of different things that don't necessarily show up in the sticker price, but that Crusoe has optimized. Things like how well you detect faults, and how quickly you replace failed nodes. For example, Crusoe was one of the first clouds to adopt any Sentinel.

22:13NVIDIA's own GPU monitoring and self-healing software for enhanced GPU, uptime, utilization, and reliability. This sets Crusoe made use of everything that NVIDIA has learned about why chips fail across all their different fleets and deployments so that Crusoe can catch faults earlier in the process. And once they identify failure, Crusoe can swap in a healthy node in less than 10 minutes.

22:35Because they're not running bare metal, Crusoe doesn't have to spend time installing an operating system or configuring drivers. They can just spin up a new VM on an already running and pre-qualified host. If you want to learn more about this, or the other reasons that Crusoe made Goaltier, go to crusoe.ai.org. It may be helpful to just see what a mux looks like, maybe like a 2-bit or a 4-bit mux. Yeah, great. So we'll take some inputs. We'll have maybe like...

23:02We'll just do a two way box. So we've got two different numbers. We've got these two inputs. And then we have a, so these are the inputs that are being selected between. And then we have a selector, which says, which can either be like, I want this one, or it could be, I want the other one. So this is a one hot encoding. So this is what we all start with.

23:40And then the output we want to produce, let's focus on this case. So this is the actual input we got. We just want to produce this guy as the result. And so very laboriously what we do is we end this bit with all of these. And so that produces like ending this bit with this row. And likewise we end this bit with this row that produces all zeros. So this was the.

24:11There's four ends here. There's four ends here. And then finally we just oar these two together. This gives a one, we oar these two together. This gives a one, we oar these two together. It gives a zero, we oar these two together and it gives a one. And so this is the four oars. So this actually ends up looking a little bit like addition, in fact. We did exactly the same set of ends here. So if we've added all of these things together, but then instead of collapsing it by using these full adder circuits. We just get a very simple collapsing with OR gates. And I guess that doesn't look like n times p. So yeah, so this was with n equals 2 inputs. In the general case we will have n rows and then we'll have p bits per row.

25:14So that gives us the N times p many AND gates. So this circuit I've described here, almost all of the cost, like 7 eighths of the cost is in the reading and writing the register file. And only a tiny fraction of the cost is in the logic unit itself. So this is the problem to solve. This essentially was the state of play.

25:39prior to the Volta generation of NVIDIA GPUs. This kind of thing is what was inside the CUDA cores. And this sort of problem statement is what motivated the introduction of tensor cores, which are more generically called systolic arrays. So if we think about how are we going to solve this problem, like we're spending almost all of our circuit area on something that we just really don't care about and is hidden to the software programmer. And the thing that we actually care about is not most of the area.

26:05Well, make this one bigger somehow while keeping this at the same size. That's the goal. So the evolution was we had baked this much into hardware in this stage. This single line is a multiply accumulate and this single thing was baked into hardware.

26:23The idea of a systolic array is to go two levels of loop up and bake this entire loop out here into hardware. And so the idea being that if we have a much bigger granularity fixed function piece of logic, maybe the taxes we pay on the input and output are much smaller. It sounds like you're suggesting that if you go up one step in the in the matrix multiply loop that there's some you can tilt the balance more towards compute than communication. That's right. So there's two effects that we're going to take advantage of here. One is just that we can do more stuff per every trip through a register file. And then the other thing we're going to take advantage of is, in fact, in some of this loop we can take advantage of, for example, some certain things staying fixed. So let's visually we're going to look at this matrix multiplication.

27:19So this portion of the loop corresponds to a matrix vector multiplication, in fact. So we'll take a matrix and multiply it by a vector. So how do we do this? We take every column gets multiplied by the vector and then summed. So we're gonna sum sort of along columns. So this 0 and 3 gets multiplied by the 3 and 7 and gets summed. And then the 1 and 2 gets multiplied by the 3 and 7 and gets summed. So.

27:48there is a multiply accumulate associated with every single one of these entries in the matrix. So we'll just draw out these four multiply accumulates. And just to make sure I understand why there's four multiply accumulates. So if each entry in the column that corresponds to the output vector is a dot product and in this case it will be like two multiplications and then the addition of those two multiplications. So like you're accumulating Yeah, so the addition, so really there's only one addition per dot product, but like we'd like to start with zero. So what we're going to aim for is to have, so we want to have quadratically more compute. We do, we have, we have got sort of x times y as much compute as we had before. But we're going to want to somehow aim for having only x times as much communication.

29:01And this is sort of the intention so that we get this advantage term going as y. So we've laid down the multiplications. We're gonna want to bring in a vector of size 2. And so that sort of already is in line with our comms target, that's fine. However, we need to somehow manage the communication of this matrix, which exceeds our budget of x. And so the idea is that, in an AI context, this matrix is actually going to stay fixed for a long period of time. And so instead of like bringing it in from the outside, so we've got some register files sitting over here, we don't want to have like the amount of stuff coming out of this register file. This is the term that we want to go sort of as X in some sense.

29:55We don't want to bring this full matrix in from the register file every every cycle because we don't have enough That would cost too much in terms of wiring from the register file and so instead we're going to store our key trick is that this matrix can be stored locally to the systolic array and so Where we'll store these numbers zero one two and three in just like a gate called a register that like physically stores these numbers and we're going to reuse these numbers over and over again for a large number of different vectors. And so the optimization here is that like the nature of matrix multiplication is you can store this like square quadratic thing directly where the logic is happening and which is like higher dimension than the

30:51or has an extra dimension compared to the inputs which you keep swapping in and out. This is the nature of what a matrix multiplication is, is that you do a lot of multiplication to get one value out. A dot product is the result of a lot of multiplications. That optimization means that you can stuff a lot of multiplication in before you get some value out of it. That's right. Just to complete the picture here of concretely how that looks.

31:19I swapped the three and the two here, three and two. So just like this zero and three is gonna multiply by the three and seven. And so we're gonna form a dot product sort of along columns here. So somehow we're gonna feed a three and a seven in here. These participate in sort of this feeds into this multiplication and also feeds into this multiplication.

31:49Likewise, the three feeds into here and also into here. And then we're going to sum along here with starting at the top of a column we feed in zeros, and then coming out the bottom we get results coming out. So just to visually see what we've got, there's a dot product that is performed along columns in a matrix. And that sort of maps exactly to what is done spatially in the systolic array here.

32:17So this is one dot product summed vertically, and this is a second dot product also summed vertically. And then what is the data that needs to go into and out of the register file? We have x amount of data that's coming out here on the output, and we also have sort of this data coming from the input, x amount of data from the input. And so with respect to the input and output vectors at least, We've met our goal of having own the X as much data going in and out of the register file. This leaves open the question of, I said that the weight matrix is stored locally in the systolic rate. How did it get there in the first place? Is at some point you need to boot your chip and populate this data, and so where did that come from?

33:10the trick is just we just do it very slowly. So we very slowly trickle feed it in into the systolic array. The sort of the simplest strategy is that we sort of run this daisy chain that says like feed a number into here and then on the next clock cycle it'll move down to the next entry of the systolic array. And so we can do that in every column in parallel and that gives us sort of this is also going to come from here and this is going to be another factor of approximately x units of bandwidth coming in. Can you just, would you mind repeating that sentence? So like, we're sort of like, we know that we're going to be bringing in numbers only rarely into the matrix. Yeah. And so.

33:54we just want to come up with any construction at all such that the amount of wiring that actually feeds into sort of crosses this boundary of the systolic array like this boundary right here. We just want to keep that bounded to X and not be not go as XY. And so a particularly simple strategy is that we sort of bring in a number into the top row of the systolic array. That's what we can do in one clock cycle and then for like for.

34:21why consecutive clock cycles are going to be bringing in the top row every time and then sort of shift all of the other rows down by one. And that keeps the wiring that needs to come from this expensive register file only down to a factor of x rather than x. I see. Okay. So there's two questions in terms of communication. There's like communication time and then there's communication bandwidth. Yes. And you're saying, since we're only going to be loading this in once, Let's minimize bandwidth because bandwidth equals die area. And let's just load it in slowly over smaller lanes because we're just going to keep this value in there for a while. Interesting. So it's interesting to me that when we were talking last time about inference across many chips, the big high level thing we're trying to optimize for is increase the amount of compute.

35:12per memory bandwidth, that is to say per communication. And here also we're trying to increase the amount of actual multiplies or actual additions relative to transporting information from registers to the logic. So in both cases, you're trying to maximize compute relative to communication. Yeah, this shows up sort of all the way up and down the stack. This is sort of close to the bottom, sort of like into the gates.

35:39There's sort of a version that's maybe even closer to the gates of just like even the precision of number format that you choose to use. We saw that same effect. There's like a square cube law or like squared versus linear term going on both in just purely the precision of this ALU but then also in terms of the size of this, the matrix. Yeah, very interesting. So this unit is sort of the next bigger unit. We had like the multiplication circuit and then On top of that, we have a pretty large systolic array. I drew it as 2 by 2, but in, for example, older TPUs, they were described as 128 by 128 of this circuit shown here. And this circuit ends up being, this is the most efficient known mechanism for the circuit for implementing a matrix multiply. I see. So we've talked about sort of

36:35It seems obvious that you should try to maximize compute relative to communication. What are non-obvious trade-offs that actually you are, you know, keep you up at night about what should we do X or should we do Y? And it's not obvious what the answer is. Yeah. So, I mean, I think most of the decisions in chip design are sizing decisions. And so already in what we've drawn so far, like, so AI chips, all have this circuit, they have a systolic array and then somewhere near at a register file providing inputs and outputs. The two sort of like even within this scope sizing questions that you have are how big should I make my systolic array and how big should I make the register file. And then the trade-off for the size of the systolic array, actually these two questions are coupled is

37:36One way to think of it is to say, I'm going to have a budget for how much, what percentage of my chip area I want to spend on data movement. So maybe I just say that I want this to be 10% and the systolic array to be 90%. And then I can size my register file. Bigger register files are more flexible. They allow me to run more, I can get more application level performance out. But then they take away from this area spent on the systolic array.

38:06I recently ran a nasty contest where I asked people to write about what I considered to be some of the biggest open questions about AI. The submission window closed last week, so I used cursor to create a couple of different interfaces to help me review the entries. One interface unautomizes submissions and hides unnecessary information. It lets me group responses by question, add notes, and record my scores. The other interface helps me review entrants who also want to be considered for the researcher role that I'm hiring for.

38:30The UI puts the applicants' essay right next to their resume and their personal website so that I can see everything at once. Cursor's hardness is really good at helping these models see and improve their UIs. I watched it render these interfaces in the built-in browser, take screenshots, click through sections, and keep iterating. At this point, Cursor is where I do most of my work. Whether I'm reading and visualizing a bunch of research papers, or coding up an interface to review applications, or making flashcards for my Blackboard lectures.

38:57Cursor just makes it very easy for an AI to look at whatever I'm looking at and help me understand it and work with me on it. So whatever you're working on, you should do it in cursor. Go to cursor.com slash dworkesh. Where does the clock cycle of a chip come in? What determines what that is? Yeah. And what is a clock cycle for the chip? So I guess at baseline, it's sort of worth observing that chips are incredibly, incredibly parallel, right? You've got a hundred billion transistors in a chip.

39:28A key thing that you need to do whenever you have massive parallelism is you need to synchronize between the different parallel units. In software, typically, you have these very expensive synchronization methods like a mutex. So one thread will finish what it's doing. It will grab a lock somewhere stored in memory and then notify the other thread that it's done. On chips, we take a very different approach and say that every nanosecond or so, all circuitry in the chip will kind of pause for a moment and then synchronize every. So it actually synchronizes every single nanosecond or so. And so that is the clock cycle. The entire chip, typically all in sort of one fell swoop, goes in lockstep to the next operation that happens. And so what this looks like in circuitry is that you will have

40:25So the clock is sort of mediated by registers, which are these storage devices that we've drawn elsewhere. And the way to think of it is that I have some storage, which is storing like a bit, which might be zero or one. And then I have some sort of cloud of logic, which maybe is like this systolic array or this multiplier or something like that. And then I've got some, and that's gonna produce some output. So my inputs, I've got a bunch of inputs feeding through this cloud of logic.

40:54And then eventually, later, there's going to be some output register that this writes to. There is a global clock signal, which drives all of these registers. And it says, at a certain instance in time when the clock strikes, whatever value happens to be on this wire at that instant, that's what's going to get stored in there. And so the sort of the challenge here is like, I would like to have my clock speed run as fast as possible because if I can run at 2 gigahertz, I can get twice as many operations done per second than if I run at 1 gigahertz. But what that ends up meaning is that I'm very sensitive to the delay through this cloud of logic because any computation that is going to happen in here needs to sort of finish before the next clock cycle hits.

41:52A major point of sort of optimization on any chip then is to make this delay from here as short as possible. Interesting. The constraint here seems to be that if you add too much logic, then you might risk missing the clock cycle. But if you don't add enough, then you're leaving potential compute on the table.

42:22Is there ever a situation where you're like, you'd take a probabilistic chance that a computation finishes and, or is it just like, no, either it's gonna finish by clock cycle or not? Yeah. In standard chip design, you margin it such that, I mean, there is a probability, but it's like many, many standard deviations, like way standard deviations out, such that for all intents and purposes, it is a reliable part. It will always meet the clock.

42:51There are some weird exceptions to that there are clock domain crossings where you go from one clock to the other clock And then you actually do have to reason about this probability, but interesting in the main path you just like you margin that such that you'll get there like 25% of the clock cycle in advance So that it's very unlikely that in this in this um the clock Where the clock synchronize I guess where the registers are This is not something you determined as a chip designer. This is sort of just like an artifact of, hey, I want whatever sequence of logic. And then the software you use to convert your Verilog into the thing you send to TSMC, that just determines like, hey, in order to make this work, you gotta kind of, you gotta put a register here, here and here to make sure that there's a, there's no one step that is like too long, such as it makes the whole clock cycle of the entire chip longer than it has to be.

43:47Yeah, so this is actually a huge part of the work of designing a chip actually is inserting them. So it is done in a combination of manually and automatically. So I mean, like just like to show you the very sort of dumb version of like what you can do here, you can take this logic and split it in half. And so like say, actually instead of just one cloud of logic, I'm going to have two smaller clouds of logic, which do the same thing, but split them up by a register. Right.

44:17feeding in like this. And this is like, if you split it like in the middle, you can hit twice the clock frequency. That's great. You get twice the performance at the cost of this extra register and so at the cost of some more storage. And so stepping back, why do we need to synchronize the whole chip? If you imagine playing Factorio or something, there's no like global clock cycle. It just should have done when it's done. There's iron on the plate. You can take it if you want. Yeah.

44:46Taking that analogy, the thing that you need to be mindful of is if I've got two different pads through some logic. So I have to do a computation like f here and then computation g here. And then they're going to come and meet for computation h somewhere here. And so there's going to be manufacturing variance here.

45:10in some chips f will take a little longer, maybe in some chips g will take a little bit longer. And so if I've got some signal that's propagating through here and the result from f and g have to sort of meet up at h, the thing that can go wrong is that f can get there early and it meets like the previous value of g or the next value of g. And h needs to know when to start. Exactly. Like when has this next iteration of... And so this explains why Different ships made at the same process node, the same like TSMC technology can have different clock cycles. Two ships made at three nanometer might have different clock cycles based on whether they were able to optimize making sure that there's no one critical path that is so long that it slows down the whole ship's clock cycle. That's right.

46:02This optimization that I showed here, this is just the sort of pipeline register insertion, it's called. We've inserted in the middle of the pipeline a register here. This is a sort of pure trade off between clock speed and an area. This is the easy case. There is a harder case too, which is sort of drawn out as a pipeline of logic here. But in other cases, you may have some.

46:29some calculation which actually feeds back in on itself. So it runs some function f and then writes back to itself like this. So for example, this might be this addition, like you've got some number that you're adding into every clock cycle. And so this could be like a plus, we're adding in some number every clock cycle.

46:52So this little circuit, essentially it's just going to sum all of the numbers that you presented on different clock cycles. And the challenge is, if this plus takes too long, what can I do? If I like split it in, if I try and put a pipeline register like right in the middle of it, like here in the middle of it, this will end up changing the computation that's done. Instead of forming a running sum of everything that comes here.

47:22I will actually have two different running sums. I'll end up having a running sum of the even numbers and a running sum of the odd numbers. So this constraint where I have a loop in my logic, which all chips have somewhere, this is actually the thing that is the hardest thing to address and sets the clock cycle. I don't understand why it would be a problem to have that, or I'm not sure even what it would mean to have a lot of register there. Because it's a sort of atomic operation, right?

47:47Yeah. Well, so plus is not really atomic. Like, I think- As we just demonstrated. Yeah. Yeah. It took a whole lot of work to do an estimation. And so, like, you can take the early parts of that work and then stick a register in the middle and then do take the late parts of that work. Okay. Yeah. And I guess it's then up to, so TSMC offers a PDK which says, hey, here's the primitives of logic that we can grant you in the chip. And it's up to them to determine that no primitive is bigger than like the clock cycle they're hoping a process node targets. But other than that, is there like, what further optimizes? Can't you just say like, hey, here's all the primitives from TSMC and keep adding registers in between the primitives as much as is needed until you get to your desired clock cycle? Yeah, as a logic designer, like the chip architect said the clock cycle. So just for one example, the primitives you get from TSMC are

48:44on the order of like hand gates or full ladders, they depends a lot on voltage and frequency and which library you choose and so on. But generally they, you can typically have about like 10 or 20 or 30 of these in a clock cycle sequentially. So these primitives are very, very fast, like 10 picoseconds or something like that.

49:05And so as a logic designer, I mean like in principle, if you literally just had like, like register and then AND gate kind of in a loop like that, you could get an insanely fast clock speed like more than four or five, six gigahertz something like that. But if you take this, this like really sort of like simple circuit and you look at the area you're spending here, like this is maybe like one, I mean, this is called one gate equivalent in size. So like unit of one in area and this thing is like unit of eight in area or something like that. And so like this is just, again, almost all of your cost has been this like synchronization or communication cost compared to the actual logic. And so this would be a case where you've gone too far. You've made your clock speed really, really fast at the cost of spending almost all of your area on pipeline registers. Interesting.

50:00What you're hinting at is a dynamic where you can have really fast clock speed, but you're not getting that much work done. Yeah, yeah. And so you can have like low latency but low bandwidth or throughput rather. Yeah, it hurts your throughput in fact because like the throughput of your chip you can think of as the product of how much do I get get done per clock cycle which is based on this area efficiency thing times how many clocks I get per second. This is actually so similar to the thing we were discussing last time about like batch size, where if you have a low batch size, then you can, any one user can receive their next token really fast, but the total number of tokens that are processed in say, an hour will be kind of lower than it could otherwise be. Yeah, exactly. You get less parallelism out if you drive your clock speed up really high. Language models are starting to compete against the best human forecasters. I sat down with two senior Jane Streeters,

50:56Ron Minsky and Dan Ponte Corvo and asked, at some point, does AI just do what Change Street does? There's a world that we should take seriously where we're going to build large language models or some other AI systems that are like strictly smarter than all humans on the planet and more capable at all cognitive tasks. Trading in particular feels to me as like kind of AGI complete, sort of like NP complete because at the end of the day, trading involves figuring out What things are worth, which means making predictions about the future? Jane Street isn't betting against AI. They just signed a $6 billion compute deal. But Ron's view is that the edge keeps moving. I have never been more desperate to hire more engineers and more traders than I am today. You know, you have the usual thing of like the other hard parts that we don't yet know how to automate. Well, that ends up being where the competitive edge lies. You can find these open positions and watch the full interview at JaneStreet.com.

51:51Okay, so I remember talking to an FPGA engineer at Chain Street, Clark, who actually helped me prep for the previous interview we did together. And he was explaining why they use FPGAs. And I imagine that for high frequency trading, throughput is less important than latency. And so having very specific control over the clock cycle in a deterministic way is the most important thing.

52:19Maybe it'd be interesting to talk about why you can't just achieve that within ASIC or why you might use an FPGA to have deterministic clock cycles for high frequency trading. Yeah, so firstly let's consider the business case for an FPGA versus an ASIC. FPGAs and ASICs use largely the same sort of conceptual model, which is that I have a series of gates built from ands or XORs, those very small primitives, connected together with a fixed clock cycle, and connected together with wires that are running in a fixed clock cycle. So anything you can express in an FPGA, you can express in an ASIC too. And it'll be about an order of magnitude cheaper and better energy efficiency on an ASIC than an FPGA.

53:13The trade-off is that the first FPGA costs you $10,000, whereas the first ASIC you make costs you $30 million because it requires an entire tape out. So the business use case for an FPGA would be that I want something that has this very deterministic latency and fast runtime and high parallelism.

53:38I'm going to change it very frequently, change what I do every month for something like that. And so then I don't want to pay the tape back cost every time. Now, how does an FPGA actually implement? It emulates the ASIC programming model, but in a fixed piece of hardware. And so how does that work actually? So what it has at the base is it's got the two components we just talked about. It's got these registers as storage devices.

54:09Then it's got these are called lots, lookup tables, which actually provide all of the gates. Then we're going to see even the third component, we then have a swarm of these registers and lots. All of these are available and then they're connected by this big set of sort of muxes. So in front of every single one of these, we've got something like one of these muxes, which selects one input from everywhere else, sort of selecting from all of these things. We've got a whole bunch of different options feeding into all of these things.

55:04So what this allows is essentially when I program my FPGA, I can say that I'm going to take all of these components and I'm going to superimpose on top of this a particular wiring which goes through this lot and then feeds into this lot and then goes to this register and then feeds into this lot or something like that. So what I've drawn in orange is how you like FPGA means field programmable gate array. This is the orange is what has been programmed in the field, whereas the white is all of the wires that must exist in the FPGA in order to actually take to make the device in the first place. What does it mean to be programmed into a field? Like programmed in the field, so like the device has been deployed in a data center, it's sitting in the field and then you can come and program. That field is like electric field, no field as in like out there in the world. And so if I see look at the how the

55:58the field programming comes out of the first lookup table and goes in the second one. How is it? Yeah, how? Like where are the wires that made that happen? Yeah. So I got a little bit like lazy in drawing all of these. Every single device here has a MUX sitting in front of it, which can select from all of the nearby circuits that are available.

56:27And so the actual configuration of the FPGA amounts to it is the MUX control. So in this MUX here, we have the data inputs, and then we have the control that selects. And so there's a little storage device sitting next to every single one of these MUXers saying, this is where you're going to source your input from.

56:55Programming it consists of like configuring every single one of these boxes. So that makes sense. What is happening inside the lookup table? Yeah. So the purpose of the lookup table, so it's going to also have a little bit of control feeding telling it what to do as well. The purpose of the lookup table is to function, to be able to configurably take the role of an AND gate or gate XOR, any of those different things. So there's many ways you could consider doing that.

57:21The way it is done in sort of traditional FPGAs is to say it will support, so it will be a lookup table will be, it will have four bits of input, one bit of output. How many different functions are there from four bits to one bit? There are 16 different functions. And so you can actually just tabulate this as like.

57:5116 different numbers, you've got a table of 0111001, 16 entries. And so what it does is this table is stored in this blue configuration bit. And then it views these four bits as binary, looks up the relevant row of the table and emits that bit. So this is a truth table view of lookup tables essentially.

58:22Okay, so the lookup table, if you think of an NAND gate or gate and OR gate, XOR gate, these are all like take as input. Those are like two input functions. Yeah. Sometimes we have like more complicated, like a three input function would be a three way XOR. Right. Or a four way XOR. And in this case, how many, it just depends how big it is, but. Typical size for lots is four input, which is sort of just a sweet spot between.

58:47There's another computer communication trade-off like here like if it has too few inputs, then you need to use more lots Yeah, if it's true, but basically the lookup table is like a truth table. It's a truth table Yeah, and with the truth table you can program in any gate you want. That's right And so if it's a lookup table just think like a programmable gate. That's right And so I mean one of the things you can do here is you can see why where the rule of thumb that an FPGA is like an order of magnitude more expensive than an ASIC comes from is to count how many gates would be inside this lookup table. So we can view this lookup table essentially as one of these muxes. And so it has to select between 16 different values. And so it is a mux with sort of n equals 16 options, p equals 1 bits. And so what we saw way earlier is that

59:48This circuit costs like n times p many gates. And so it's like, so it costs like n times p equals 16 and gates and also 16 ORs. This circuit being the MUX. Yeah, exactly, the MUX. The MUX is the core of the circuit. The MUX that goes into the lookup table. So the lookup table itself, you can think of as being actually a big MUX that like selects from all 16 rows down to one output. Yeah, okay. That is the lookup table.

1:00:16But the way you've drawn it here, there's like a MUX and then a lookup table. It's MUX is all the way down. So I mean, there is a second MUX that is inside here. This MUX is this MUX. Got it. OK. And then the other MUX is just saying where it came from in this sort of mess of case. Right. And then the second MUX is, OK, now you have one value, but that value is still a 4-bit value.

1:00:41Yeah. So I've selected four bits from the soup. Right. And then I use those four bits to select which entry in the lookup table I'm going to use. Right. Okay. So like, suppose in the first box there's like eight nearby, you're pulling from eight nearby registers as input. And so that's like a total of like 32 bits going in. And then out of that, four bits come out.

1:01:07Those four bits go into the second MUX, which is inside the lookup table. So actually, I would say in, yeah, in this case, these registers are single bit registers. So if there are eight, like eight nearby registers and lookup tables, then I have eight bits total coming in, in nearby. I select from eight down to four different values. So there's actually like four different MUXes, one associated with each of these input, like little MUX associated with each of these input bits. Each of them is selecting one out of eight. And what are those A coming from?

1:01:39nearby registers and other lots. And each register is one bit. Yes, yeah. And so I guess AMD or whoever makes these FEJs still has to be opinionated about what registers are connected with registers. And then you can program in the actual gates, but they add a wire in the connection, like the communication topology, right?

1:02:03Yeah. So there's the sort of like, you get flexibility in a local grain thing. There's a sort of nearby neighborhood where you can select from. But then more grossly, like more costly, longer distance connections, they form an opinion. Right. Yeah. And the reason it's 10x lower is why? So if you look at the cost of like building this lookup table, it's like 32 gates. Yeah. And then it can give me the equivalent of like what's an interesting thing I can do here, I can do a four-way AND gate. And so that's like, I'm using 32 gates of lookup table to sort of implement like a four-way AND means like, what is a four-way AND? I would do like AND, AND, and then AND of AND. So like this is a circuit that I could implement in an ASIC directly using these three AND gates. But using a lot, I can also implement it, but it's going to take like these 32 gates instead of three.

1:02:57And so the overhead is really coming from the, like, the fact that the lookup table, the MUX and the lookup table is, there's a more concise way to describe a truth table than listing out every single possible combination of inputs, which is just to, like, write out the gate. Yeah, like, to, like, place down the polysilicon and the lines. That's right, that's right. Interesting. One important point he made to me is that the reason they prefer FPGAs to CPUs is because they get deterministic clock cycles. They know what a pack will come in and go out. Why is it not a guarantee in CPUs? So you can actually design a CPU that has deterministic latency as well. And in fact, the processes that are inside a lot of AI chips actually also have deterministic latency too. Grock has advertised this. TPUs have that in the core as well.

1:03:57The challenge is getting sort of deterministic latency and high speed at the same time. And so where does the non-determinism in latency come from? Non-deterministic latency comes from specific design choices in a CPU. It's actually possible to remove those design choices and make a CPU that has deterministic latency. Those are not very attractive in the market and so people don't make those CPUs anymore.

1:04:27But actually in some sense, deterministic latency is maybe a sort of a simpler designing starting point. And then some chip designers have added things into it to be non-deterministic. To take a concrete example of that, probably the most important example is on a CPU just like the CPU cache itself.

1:04:55In a CPU, you have the CPU, this is the CPU die itself and then there's a memory off on the side. This is the DDR memory off on the side. And then you have a cache system here inside it is the cache that sort of remembers recent accesses to DDR and stores them. And so.

1:05:19When I'm running through my CPU instructions, every time I have an instruction that accesses memory, it first checks in cache, was the data stored in cache, and then if not, it goes, it fetches out to DDR. This is a huge optimization. The cache is like two orders of magnitude faster than the DDR. If you never use the cache, basically all programs would run 100 times slower. So the presence of a cache is absolutely necessary for a CPU to run at reasonable speed.

1:05:50But whether or not you get a cache hit is dependent on the sort of ambient environment of the CPU, like what other programs are running, what has run recently, what is the random number generator inside the cache system doing. And so that is a big source of non-determinist in the runtime of a CPU. So this is sort of the memory system for a CPU.

1:06:12The the big thing that you can do differently is Instead of having the hardware say I'm gonna like read read memory and then decide the hardware decides whether or not it comes comes comes from cash or not You can actually bake this in this decision into software. So a different design philosophy is is to So and you see this in maybe for example TPUs The the TPU instead has I mean I'll draw the same diagram, but I'll call it a scratch pad and so The main difference is, so this would be like a TPU and then like HBM in this case rather than DDR, but it's still an off-chip memory. And instead of like the software saying first access like memory and then the hardware decides, you've got some instructions that go here. This is like one kind of instruction and then a totally different kind of instruction that goes to HBM. And so this style is generically known as scratch pad.

1:07:11instead of cache, the key distinction being that you have one kind of instruction that says, read or write scratchpad, and a totally different instruction that says, read or write HBM. So is scratchpad being the cache? Yeah, this thing here is the scratchpad. So stepping way back, people say computers have the quote unquote John Moyn von Neumann architecture where there's this serial processing of information. And maybe just because we've been talking about a parallel.

1:07:41accelerators, but I just don't like the FUGA is super parallel. The the kinds of AI accelerators, TPUs are super parallel. Even CPUs are super parallel if you think about all the cores they have. And so is it actually like in what sense is modern hardware actually the von Neumann architecture? Is it actually a fair way to describe modern hardware?

1:08:03I think it's a fair way to describe CPUs like just the amount of parallelism like on a CPU the amount of parallelism yet is about a hundred cores times maybe like 16-way vector unit so 106 about a thousand-way parallelism on a CPU Yeah, is it one question is what is the there is a die that is being used for the CPU and if there's fewer threads and just as a matter of like transistor Voltages or like switching on and off Is it just that there's like literally one control flow, like a small part of the die where like voltages are switching on and off? Or like, in what, how do you actually occupy the die area of a CPU if there's, as opposed to- If there's so few cores, like what am I spending a lot of dying in there? The cores are just much bigger and more complicated. So, I mean like, so I guess we should compare like a CPU core which takes up one hundredth of the die to like-

1:09:00I mean, to a lot, like a lot is just only these 16 gates. So, like it's clear why there are so many more lots in an FPGA than cores in a CPU. But then sort of maybe the, like why are there more CUDA cores, for example, than CPU cores? I think would be like why, what's the difference between a CPU and a GPU or something like that would be a big difference. Inside the CPU, you have So one big use of, so the sort of the top unit uses of area in a site of CPU are the cache. Very little is actually the ALUs. Like mostly it's like these register files rather than the logic units. And then both of these things have equivalents in a GPU and so that's not a big difference. But the thing that does not have an equivalent in a GPU is the sort of this branch predictor. And so there is a whole.

1:09:56big area in the CPU which is sort of just a whole bunch of predictors that are saying, when will my next branch be and where is the branch target for that? And so stripping a lot of that out as well as sort of making these register files tighter in a sense is driving a lot of where the GPU gains on the CPU. And what is the branch predictor to execute both branches at once or what does it do?

1:10:24So the issue is that when I've got a series of instructions like instructions, instructions, instructions, instructions, if I have a branch like here, if this instruction is branch, the actual processing step of processing an instruction takes a really long amount of time. It takes maybe five nanoseconds or something like that. So the time to actually notice that I've got a branch and then evaluate the Boolean, whether it's true, and then update the program counter to the new target, and then read from the instruction memory for that. That could take like actually five nanoseconds to finish. So in reality, this may finish some way down here. But I want to run a clock speed that is much faster than what five nanoseconds allows. Like five nanoseconds is 200 megahertz clock speed. I would like to run it one or two gigahertz or something like that.

1:11:25I need to run other instructions while the branch is being evaluated. I really just want to keep running the following instructions that happen after me, but that might have been wrong. If the branch ended up being taken, then I need to know that instead of evaluating these instructions, I actually need to jump to wherever the target is and run these instructions instead. So the purpose of the branch predictor is like, genuinely to predict based on like before you even get to the destruction to be like five cycles earlier to predict there was going to be a branch that's going to happen. So if I think about how the brain works versus what you're describing here, at a high level the differences might be that while you can do structured sparsity in these accelerators and then save yourself some area that you would have otherwise had to dedicate to these gates, in the brain there's unstructured sparsity.

1:12:21you know, any neuron can connect to any other neuron and not in like ways where they'd be column-lined or whatever. Then there's the fact that memory and computer are co-located. I guess you could say in a way the memory and computer are co-located on... This is exactly the co-location in some sense of the memory and computer. That's right, that's right, yeah. Yes, maybe that actually isn't a big difference. And the other, maybe a big difference is that the clock cycle on the brain is much slower than on computers.

1:12:51And partly that's to preserve energy because the faster the clock cycle the bigger the voltage Needs to be in order to identify For the signal to settle and to like identify what state of transistor is that I don't know if you have other high-level takes about like how Any commentary on what you know what with the brain might be doing versus how these ships work? Yeah, I mean so so let's take the clock speed one first actually yeah the Clock speed is quite high on on a chip because that I mean drives higher throughput Like when we compare a like a GPU running some some workload it's running batch size a thousand or something like that Whereas like the brain is not running batch size thousand. It's only one of me and so you could sort of imagine saying well take a GPU and like instead of running at a gigahertz run at a megahertz or something like that and and that would start to look maybe a little bit more like like

1:13:53sort of equivalent things that you're talking about in the brain. There is in the way that silicon works there are like that does not give you an 1000x advantage in energy efficiency. So what it ends up looking like is you can like you sort of just end up running this circuit.

1:14:17once to stabilization and then it'll sit idle for a long period of time. It doesn't consume a lot of energy while it's sitting idle because most of the energy is consumed in sort of toggling bits from zero to one and back. So actually let's talk about the energy consumption of a circuit like this. The way to think of a bit being stored is you've actually deposited some charge in a capacitor somewhere, sitting somewhere in the chip implicitly.

1:14:46It becomes charged when it becomes a 1 and then it becomes discharged when it next goes to a 0. And that cycle of like charging the capacitor and then dumping that charge out to ground, that is where the energy is consumed. This is called the dynamic or switching power. This is most of the energy consumption of a chip. There is some other energy consumption just coming from the fact that insulators aren't perfect insulators, but we'll discuss that. Most of the energy consumption actually comes from just the charging and discharging of like toggling from zero to one and back to zero. So if you run a chip much slower and you only clock at once every thousand clock cycles or something, you will have a thousand times fewer transitions. It'll be about a thousand times less energy consumption, but not a substantial advantage in energy efficiency. Okay, so you described how a TPU works at a high level.

1:15:37What is the difference at high level between how a GPU and a TPU work? Yeah, so I mean, I think there's sort of a high level organization principle that is different. And then there's sort of inside the cores what are different. But we'll look sort of outside the like at the high level. So we'll take a GPU and a TPU and what is like sort of the top level block structure look like. If you think of this as the whole chip in each case, The organization of the GPU is mostly a bunch of almost identical units, which are these are the SMs. And then they've got an L2 memory in the middle, and then a bunch more of these SMs on the bottom. And so there's sort of this fairly regular grid of cores.

1:16:34And then if we look at a TPU in comparison, you end up with much coarser grained units of logic. And so you end up with something like some large number of maybe just a few matrix units. These are the big systolic arrays. And then in the middle you've got some vector units.

1:17:03And then you've got your matrix units at the bottom. So now sort of like matrix units with a vector unit in the middle, sort of this is the whole TPU chip. You can sort of think of scaling this thing down into a really tiny unit with a smaller matrix unit, smaller vector unit. And that is sort of what an SM is. So sort of at a very high level point of view, the GPU has a lot of tiny, tiny TPUs sort of tiled across the whole chip. Oh, interesting. So like you're suggesting the tensor core within a streaming SM is analogous to an MXU. Yeah, it's very, very similar. Yeah. I see. And so if you had more like, more lack of structure, having a bunch of tiny TPUs makes a lot of sense. Whereas if you kind of just have like huge, major multiplications, you're like, why don't we just

1:17:58Why don't we avoid the cost of having the individual SMs with their own registers and work schedulers and things like that? Why don't we just make a huge thing and amortize those costs?

1:18:11across the whole thing. And I mean I think this shows up in how large you can grow things. We've sort of seen this theme like especially with the systolic array where largest systolic array amortizes the register file costs better. This sort of design allows you to have largest systolic arrays, whereas the sort of GPU design constrains you to having small units of everything. There is a trade-off however. There ends up being because of this sort of coarse-grained separation of things there. You need to move a lot of data from the vector unit to the matrix units. And so you need to move a lot of data through a sort of two lines of parameter here. Whereas if you sort of look at the equivalent thing here, you've got vector units everywhere. And you need to move data through this line, through this line, through this line, through this line, through this line.

1:19:06So the amount of data you can move between a vector unit and matrix unit is actually much higher in a GPU than in a TPU because instead of having to move all the data through these just two lines, you're moving all these data through 16 lines or something of wiring instead in a GPU. Right, but also you might have to move across the last area.

1:19:32which is also a saving, like it's an energy saving. So data ends up moving like, if you can operate entirely within an SM, the data movement is much smaller, but then the moment you want to operate across SMs, it becomes sort of more complicated and expensive. So you don't have to comment, but one might expect that a thing that Maddox might try to do is to get the GPU-like smaller structure of systolic arrays surrounded by SRAM, but also at the same time, make it so that the things you need in an SM to support the CUDA architecture, but take a bunch of space, you might discard. Yeah. We've talked publicly about something which we call a sysplitable systolic array, which is sort of, in some sense, you can think of as big systolic arrays that can be small systolic arrays as well. Cool. Okay, I think this is a good note to close on. Reiner, thank you so much. Thanks, Rakesh.